II鈩?/div>
microprocessor chip sets. The device features
18 low skew outputs optimized to drive the clock inputs of standard
unbuffered SDRAM modules. Standard unbuffered SDRAM modules
require four clocks per module allowing for the device to drive up to four
modules. The output buffers have been optimized to drive the load
presented by the SDRAM module.
The MPC9140 provides output shut off capabilities via an I2C serial
port for applications which plan to use fewer than four modules and desire
to minimize the power dissipation of the chip. Every output clock can be
individually enabled/disabled through fields in the I2C control registers.
After power up the default state is all outputs enabled. In applications
where this default state is acceptable the I2C ports need not be exercised.
MPC9140
1:18 LVCMOS
FANOUT BUFFER
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Supports Intel Pentium鈩?and Pentium
II
Processor Architectures
18 Skew Controlled 3.3V Compatible SDRAM Clocks
I2C Serial Bus Interface
Extensive Output Enable Control Capability
Space Efficient 48鈥揕ead SSOP Package
Operating Temperature Range of 0擄C to 70擄C
3.3V
鹵
5% Power Supply
NC
NC
VDD
SDRAM0
SDRAM1
VSS
VDD
SDRAM2
SDRAM3
VSS
BUF_IN
VDD2
SDRAM4
SDRAM5
VSS
VDD
SDRAM6
SDRAM7
VSS
VDD
SDRAM16
VSS
VDD
SDATA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
SD SUFFIX
48鈥揕EAD PLASTIC SSOP PACKAGE
CASE 1215鈥?1
NC
NC
VDD
SDRAM15
SDRAM14
VSS
VDD
SDRAM13
SDRAM12
VSS
OE
VDD
SDRAM11
SDRAM10
VSS
VDD
SDRAM9
SDRAM8
VSS
VDD
SDRAM17
VSS
VSS
SCLOCK
0
1
High鈥揨
1x BUF_IN
FUNCTION TABLE
OE
V1, V2
Figure 1. 48鈥揕ead Pinout
(Top View)
This document contains information on a product under development. Motorola reserves the right to change or
discontinue this product without notice.
6/97
漏
Motorola, Inc. 1997
1
REV 0.2
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