鈮?/div>
1碌A at V
OL
, V
OH
November 1997
Features
鈥?Typical Propagation Delay = 17ns at V
CC
= 5V,
C
L
= 15pF, T
A
= 25
o
C
鈥?Replaces 74LS180 Types
鈥?Easily Cascadable
鈥?Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
鈥?Wide Operating Temperature Range . . . -55
o
C to 125
o
C
鈥?Balanced Propagation Delay and Transition Times
鈥?Signi鏗乧ant Power Reduction Compared to LSTTL
Logic ICs
鈥?HC Types
- 2V to 6V Operation
- High Noise Immunity: N
IL
= 30%, N
IH
= 30% of V
CC
[ /Title
(CD74
HC280
,
CD74
HCT28
0)
/Sub-
ject
(High
Speed
CMOS
Logic
9-Bit
Odd/E
ven
Parity
Description
The Harris CD74HC280 and CD74HCT280 are 9-bit
odd/even parity, generator checker devices. Both even and
odd parity outputs are available for checking or generating
parity for words up to nine bits long. Even parity is indicated
(危E output is high) when an even number of data inputs is
high. Odd parity is indicated (危O output is high) when an odd
number of data inputs is high. Parity checking for words larger
than 9 bits can be accomplished by tying the
危E
output to any
input of an additional HC/HCT280 parity checker.
Ordering Information
Functional Diagram
Pinout
CD74HC280, CD74HCT280
(PDIP)
TOP VIEW
I6 1
I7 2
NC 3
I8 4
危E
5
危O
6
GND 7
14 V
CC
13 I5
12 I4
11 I3
10 I2
9 I1
8 I0
I0
I1
I2
I3
I4
I5
I6
I7
I8
8
9
10
5
11
12
6
13
1
2
4
GND = 7
V
CC
= 14
NC = 3
鈭?/div>
EVEN
鈭?/div>
ODD
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
漏
Harris Corporation 1997
File Number
1669.1
1
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2
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