今天得到軟件x-hdl，整個軟件不大，好象是2.7M,有興趣的可以來這里：
ftp://218.64.19.133
文件1(intall)：xhdl3.1.42.exe
文件2(crack) ：X-HDL.v3.1.30.zip（我現(xiàn)在只有X-HDL.v3.1.30的，沒法，先用它吧）。
據(jù)介紹，用它可以把你的VHDL設(shè)計文件轉(zhuǎn)換為
VERILOG，也可以把VERILOG===》VHDL。我安裝后馬上試了一下，
以下是我次試用的VERILOG，一個十進制計數(shù)器：
module count10(out,clk);
output out;
input clk;
reg out;
reg [2:0] count;

always @(posedge clk )
begin
count = count + 1;
if( count == 5 )
begin
count = 0;
out =!out;
end
end
endmodule

下面是用它轉(zhuǎn)換VHDL的結(jié)果：---------------------------------------------------------------------------------------------
--
-- VHDL file generated by X-HDL - Revision 3.1.42
-- Wed Oct 31 15:00:13 2001
--
-- Input file : c:/My Documents/XXXXXX/count5.v
-- Design name : count5
-- Author : 112
-- Company : 112
--
-- DescripTIon :
--
--
----------------------------------------------------------------------------------------------
--

ENTITY count5 IS
PORT (
out_xhdl1 : OUT std_logic;
clk : IN std_logic);
END count5;

ARCHITECTURE translated OF count5 IS


SIGNAL count : std_logic_vector(2 DOWNTO 0);
SIGNAL out_xhdl1_xhdl2 : std_logic;

BEGIN
out_xhdl1 <= out_xhdl1_xhdl2;

PROCESS
BEGIN
WAIT UNTIL (clk'EVENT AND clk = '1');
count <= count + "001";
IF (count = "101") THEN
count <= "000";
out_xhdl1_xhdl2 <= NOT out_xhdl1_xhdl2;
END IF;
END PROCESS;

END translated;